`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   14:48:01 09/12/2012
// Design Name:   Divider
// Module Name:   C:/Users/Maria Victoria/workspace/projecto3/DividerVerification.v
// Project Name:  projecto3
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: Divider
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module DividerVerification;

	// Inputs
	reg clock_i;
	reg reset_i;

	// Outputs
	wire clock1hz;
	wire clockhalfhz;

	// Instantiate the Unit Under Test (UUT)
	Divider uut (
		.clock_i(clock_i), 
		.reset_i(reset_i), 
		.clock1hz(clock1hz), 
		.clockhalfhz(clockhalfhz)
	);

	initial begin
		// Initialize Inputs
		clock_i = 0;
		reset_i = 0;

		// Wait 100 ns for global reset to finish        
		// Add stimulus here

	end
   always #20 clock_i= ~clock_i;
endmodule

